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Testbench Operation
8
Three testbenches are provided with CorePCIF.
? VHDL verification testbench: Complex testbench that verifies core operation. This testbench exercises all the features
of the core. Actel recommends not modifying this testbench. This VHDL testbench can be used to simulate the Verilog
version of the core if a mixed-mode simulator is available.
? VHDL user testbench: Simple-to-use testbench written in VHDL. This testbench is intended for customer
modification.
? Verilog user testbench: Simple-to-use testbench written in Verilog. This testbench is intended for customer
modification.
Verification Testbench
The verification testbench consists of a master test controller, a PCI monitor, an arbiter, and devices under test. The test
master is used for generating configuration cycles and performing basic read-and-write tests of the macro when
operating as a PCI Target. The PCI monitor checks for and flags abnormal PCI bus activity. The arbiter determines
PCI bus ownership.
Backend
Memory and
Control
Core 1
PCI
Arbiter
Backend
Memory and
Control
Core 2
PCI Bus
Backend
Memory and
Control
Core N–2
Backend
Memory and
Control
Core N–1
Test Master
Fast Master
PCI Monitor
PCI Target
Procedural Testbench
Figure 8-1 · The Verification Testbench
The verification testbench supports up to 14 cores connected to the PCI bus. Each core is configured differently,
allowing multiple core configurations to be tested at the same time. Table 8-1 on page 118 details the core configurations
used in the standard testbench.
v4.0
117
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相关PDF资料
COREU1LL-AR IP MODULE COREU1LL
COREU1PHY-AR IP MODULE COREU1PHY
CORR-8BIT-XM-UT2 SITE LICENSE IP CORRELATOR XP
CP2-GSA-L CONN SHIELD LOWER TYPE A 22
CP2-HSA110-1 CONN SHROUD CPCI 2MM TYPE A 22
CP2-HSC055-4 CONN SHROUD CPCI 2MM TYPE C 11
CP2-K3567-SR-F COMPACT PCI - MISC
CP2105EK KIT EVAL FOR CP2105
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